Digital Systems Testing And Testable Design Solution High Quality Today
Miron Abramovici's Digital Systems Testing and Testable Design
Here is an interesting look at the intersection of high-quality digital testing and testable design. 1. The "DFT" Revolution: Designing for the Unexpected Design for Testability (DFT) You needed to force a node to a
This was the ancient war of digital testing: controllability and observability . You needed to force a node to a specific state (controllability) and then watch its effect on the outside world (observability). Athena was failing both. This allows for testing interconnections between chips on
In the context of digital systems, a high-quality testable design solution is defined by specific, measurable metrics: Without rigorous testing
Standardized as IEEE 1149.1, Boundary Scan places test cells around the I/O pins of a chip. This allows for testing interconnections between chips on a printed circuit board (PCB) without needing physical probes (bed of nails), which is crucial for modern, densely packed boards.
DFT is the discipline of adding extra hardware to make a system more testable. The overhead (area, power, performance) is justified by orders-of-magnitude reduction in test cost and time.
In the early days of digital logic, testing a circuit was straightforward: apply a set of input vectors and compare the outputs to a truth table. Today, a modern microprocessor contains billions of transistors. Manufacturing defects—such as shorts, opens, process variations, and bridging faults—are inevitable. Without rigorous testing, defective chips would reach end-users, causing system failures, safety hazards (in automotive or medical devices), and massive financial losses.
